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5 months ago
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Senior Engineers – Verification Engineering


STS Technical Services
Location: Denver
Job type: Permanent
Sector: Manufacturing
Category: Engineers Jobs
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STS Technical Services, in partnership with SEAKR Engineering, is Hiring Senior Engineers – Verification Engineering in Denver, Colorado!

About The Company:

SEAKR Engineering is a Colorado company and aerospace innovator. They build, design and manufacture advanced electronics for space applications including solar system exploration, space-based U.S. defense support and commercial satellite communications. SEAKR offers a casual work culture in a fast-paced engineering environment. This provides our engineers with the opportunity to contribute real solutions to real-world engineering challenges. If you’re ready to join one of the most talented engineering organizations in the aerospace industry, SEAKR is the place for you.

Position Summary:

Seeking a Verification Engineer who is responsible for developing verification and simulation strategies, conducting design reviews, creating a digital test plan and providing coverage metrics. The engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test.

Required Qualifications:

* The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements

* Ability to architect and construct full test environments for complex devices using UVM, including coverage, is required

* The candidate shall be capable of diagnosing sophisticated test failures and filing results, and be capable of analyzing code coverage to adjust agent sequence behavior

* Ability to provide direction to less senior verification engineers is required

* Ability to lead a team of verification engineers to fully verify a device is required

* Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting is required

* Ability to analyze Verilog RTL to diagnose test failures is required

* Ability to analyze VHDL is a plus

* Must be able to work effectively under pressure to meet tight deadlines

* Experience verifying DSP related designs a plus

* A Bachelor’s degree in Electrical Engineering or Computer Science and at least 10 years of verification engineering experience are required.

* A Master’s Degree is preferred

* U.S. Citizenship required

Since this is a direct hire job, our client will provide a full benefits package to you. If you would like to learn more about that package, please call.

Thanks for taking the time, and we look forward to hearing from you soon.
STS Technical Services, in partnership with SEAKR Engineering, is Hiring Senior Engineers – Verification Engineering in Denver, Colorado!

About The Company:

SEAKR Engineering is a Colorado company and aerospace innovator. They build, design and manufacture advanced electronics for space applications including solar system exploration, space-based U.S. defense support and commercial satellite communications. SEAKR offers a casual work culture in a fast-paced engineering environment. This provides our engineers with the opportunity to contribute real solutions to real-world engineering challenges. If you’re ready to join one of the most talented engineering organizations in the aerospace industry, SEAKR is the place for you.

Position Summary:

Seeking a Verification Engineer who is responsible for developing verification and simulation strategies, conducting design reviews, creating a digital test plan and providing coverage metrics. The engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test.

Required Qualifications:

* The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements

* Ability to architect and construct full test environments for complex devices using UVM, including coverage, is required

* The candidate shall be capable of diagnosing sophisticated test failures and filing results, and be capable of analyzing code coverage to adjust agent sequence behavior

* Ability to provide direction to less senior verification engineers is required

* Ability to lead a team of verification engineers to fully verify a device is required

* Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting is required

* Ability to analyze Verilog RTL to diagnose test failures is required

* Ability to analyze VHDL is a plus

* Must be able to work effectively under pressure to meet tight deadlines

* Experience verifying DSP related designs a plus

* A Bachelor’s degree in Electrical Engineering or Computer Science and at least 10 years of verification engineering experience are required.

* A Master’s Degree is preferred

* U.S. Citizenship required

Since this is a direct hire job, our client will provide a full benefits package to you. If you would like to learn more about that package, please call.

Thanks for taking the time, and we look forward to hearing from you soon.

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