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8 months ago
United Technologies
Location: Phoenix
Job type: Permanent
Sector: Manufacturing
Category: Supervisors
Staff Eng, FPGA Verification & Validation Lead

Business Unit UTC Aerospace Systems
Job ID 41071BR Date posted 01/18/City Phoenix
State Arizona
Country United States

Senior Electrical Engineer – FPGA Verification and Validation Lead
UTC Aerospace Systems is one of the world's largest suppliers of technologically advanced aerospace and defense products. We are a premier designer and manufacturer of integrated aerospace systems for nearly everything that flies - from tip to tail - for commercial, regional, corporate and military aircraft applications. We are also a major supplier to international space programs.
The UTC Aerospace Systems’ (UTAS) Electronic Systems Center (ESC) is a strategic business unit headquartered in scenic Phoenix, AZ. The ESC supports a wide variety of UTAS aerospace products with state-of-the-art facilities and expertise. The ESC team designs, tests, builds, and supports electronic components and systems for all parts of the UTC Enterprise. The scope of our systems is usually around the electronic components within larger systems. Examples include electric actuator and motor controllers, where these controllers consist of hardware, firmware, and software and interface with actuators, motors, and other electronic controllers and computers within the larger aircraft system.

We recruit the best talent and use the best processes to solve some of the industry's greatest challenges - safely, ethically and responsibly. We are looking for a highly motivated individual to join our team. How our people perform is as important as how our products operate.

Position Overview:
The Senior Verification & Validation (V&V) Engineer will be part of the key FPGA Design team and is responsible for the end-to-end verification and delivery of FPGAs. S/he will develop verification architectures, set strategy for verification methodology and EDA selection, for verification of complex FPGA designs. The V&V Engineer will be responsible for developing test plans, developing /enhancing verification framework, metric driven verification (code and functional coverage), modeling (C++, System C), HW/SW co-simulation, and test vector generation. Additionally, the Verification Engineer will be involved from concept definition through initial FPGA bring up, Integration and Test, and product release. S/he will also work with a team of local and overseas HDL developers to complete CPLD and FPGA designs, simulations, synthesis, and lab integration.

Primary Responsibilities:

* Lead a team of FPGA designers to ensure efficient work, status, problem resolution and customer satisfaction.
* Provide training as required to ensure compliance with DO-254 and other industry standards and certification standards.
* Follow DO-254 Level A program planning documentation, and ensure CPLD/FPGA design team adheres to the plans.
* Capture and document the customer flowed down functional requirements, and develop and document the derived requirements for FPGAs.
* Design FPGA architectural diagrams; develop VHDL to implement the design critical functionality.
* Develop sub functions and test benches.
* Perform engineering timing simulations and functional analysis.
* Interface with the V&V team and Quality Engineers to support the creation of the DO-254.
* Most critically, the ideal candidate will be able to prioritize multiple requests in a fast-paced environment with impeccable attention to detail and accuracy while maintaining a pleasant and "can do" attitude.
The successful candidate must be willing to pitch in and do whatever is necessary to get the job done right.
* In depth experienced simulating HDL and using Mentor Modelsim.
* Experience with Actel, Xilinx, FPGAs and development tools.
* Excellent FPGA lab integration and troubleshooting knowledge.
* Experience with timing closure techniques
* Experience of full development cycle (including system and block level testing)
* Strong understanding of software and hardware interaction
* Strong Ability to design test benches.
* Experience with Mentor HDL Designer, Precision Synthesis, Questa and Req Tracer.
* Experience with DO-254 Level A design methodology for Complex Electronic Hardware.
* Must display excellent teamwork, team leadership and problem solving skills.

Critical Competencies:
Team Leadership
Drive for Results
Interpersonal Savvy
Commitment to Continuous Improvement
Effective Teamwork

Education: Qualifications:
To be considered, responses must include information meeting EDUCATION and EXPERIENCE requirements.

* BS degree in Electrical Engineering or Computer Engineering; Computer Science is required.
* At least six (or four with Masters) years’ experience in VHDL or Verilog design for CPLDs or FPGAs in an Aerospace environment.

United Technologies Corporation is An Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age or any other federally protected class.


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